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cy8c20534, CY8C20434 cy8c20334, cy8c20234 psoc? mixed-signal array cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-05356 rev. *d revised november 12, 2007 features low power capsense block ? configurable capacitive sensing elements ? supports combination of capsense buttons, sliders, touch - pads, and proximity sensors powerful harvard architecture processor ? m8c processor speeds running up to 12 mhz ? low power at high speed ? 2.4v to 5.25v operating voltage ? industrial temperature range: -40c to +85c flexible on-chip memory ? 8k flash program storage 50,000 erase/write cycles ? 512 bytes sram data storage ? partial flash updates ? flexible protection modes ? interrupt controller ? in-system serial programming (issp) complete development tools ? free development tool (psoc designer?) ? full featured, in-circuit emulator, and programmer ? full speed emulation ? complex breakpoint structure ? 128k trace memory precision, programmable clocking ? internal 5.0% 6/12 mhz main oscillator ? internal low speed oscillator at 32 khz for watchdog and sleep programmable pin configurations ? pull up, high z, open drain, and cmos drive modes on all gpio ? up to 28 analog inputs on gpio ? configurable inputs on all gpio ? selectable, regulated digital io on port 1 ? 3.0v, 20 ma total port 1 source current ? 5 ma strong drive mode on port 1 versatile analog mux ? common internal analog bus ? simultaneous connection of io combinations ? comparator noise immunity ? low dropout voltage regulator for the analog array additional system resources ? configurable communication speeds ?i 2 c: selectable to 50 khz, 100 khz, or 400 khz ? spi: configurable between 46.9 khz and 3 mhz ? i 2 c? slave ? spi master and spi slave ? watchdog and sleep timers ? internal voltage reference ? integrated supervisory circuit logic block diagram sram 512 bytes system bus interrupt controller 6/12 mhz internal main oscillator global analog interconnect psoc core cpu core (m8c) srom flash 8k system resources analog system analog ref. i2c slave/spi master-slave por and lvd system resets port 1 port 0 sleep and watchdog analog mux port 3 port 2 capsense block config ldo [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 2 of 34 psoc functional overview the psoc? family consists of many mixed signal arrays with on-chip controller devices. these devices are designed to replace multiple traditional mcu based system components with one low cost single chip programmable component. a psoc device includes configurable analog and digital blocks and programmable interconnect. this architecture enables the user to create customized peri pheral configurations to match the requirements of each individua l application. additionally, a fast cpu, flash program memory, sram data memory, and configurable io are included in a range of convenient pinouts. the psoc architecture for this device family, as shown in figure 1 , is comprised of three main areas: the core, the sys - tem resources, and the capsense analog system. a common versatile bus enables connection between io and the analog system. each cy8c20x34 psoc dev ice includes a dedicated capsense block that provides sensing and scanning control cir - cuitry for capacitive sensing applications. depending on the psoc package, up to 28 general purpose io (gpio) are also included. the gpio provide access to the mcu and analog mux. the psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, imo (internal main oscillator), and ilo (inter nal low speed oscillator). the cpu core, called the m8c, is a powerful processor with speeds up to 12 mhz. the m8c is a two mips, 8-bit harvard architec - ture microprocessor. system resources provide additional capability such as a con - figurable i 2 c slave or spi master-slave communication inter - face and various system resets supported by the m8c. the analog system is composed of the capsense psoc block and an internal 1.8v analog reference. together they support capacitive sensing of up to 28 inputs. the capsense analog system the analog system contains the capacitive sensing hardware. several hardware algorithms ar e supported. this hardware per - forms capacitive sensing and scanning without requiring exter - nal components. capacitive sensing is configurable on each gpio pin. scanning of enabled capsense pins is completed quickly and easily across multiple ports. figure 1. analog system block diagram the analog multiplexer system the analog mux bus connects to every gpio pin. pins are con - nected to the bus individually or in any combination. the bus also connects to the analog system for analysis with the capsense block comparator. switch control logic enables sele cted pins to precharge continu - ously under hardware control. this enables capacitive mea - surement for applications such as touch sensing. other multiplexer applications include: complex capacitive sensing inte rfaces such as sliders and touch pads chip-wide mux that enables analog input from any io pin crosspoint connection between any io pin combinations when designing capacitive sensing applications, refer to the lat - est signal-to-noise signal level requirements application notes, found under http://www.cypress.com >> design resources >> application notes. in general, unless other - wise noted in the relevant app lication notes, the minimum sig - nal-to-noise ratio (snr) requirement for capsense applications is 5:1. id ac reference buffer vr cinternal analog global bus cap sense counters comparator mux mux refs capsense clock select relaxation o scillator (ro) csclk imo [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 3 of 34 additional system resources system resources provide additional capability useful to com - plete systems. addition al resources includ e low voltage detec - tion and power on reset. brief statements describing the merits of each system resource are presented below. the i 2 c slave or spi master-slave module provides 50/100/400 khz communication over two wires. spi communication over three or four wires run at speeds of 46.9 khz to 3 mhz (lower for a slower system clock). low voltage detection (lvd) interrupts signal the application of falling voltage levels, while the advanced por (power on reset) circuit eliminates t he need for a system supervisor. an internal 1.8v reference provides an absolute reference for capacitive sensing. the 5v maximum input, 3v fix ed output, low dropout regulator (ldo) provides regulation for ios. a register controlled bypass mode enables the user to disable the ldo. getting started to understand the psoc silicon r ead this datasheet and use the psoc designer integrated deve lopment environment (ide). this datasheet is an overview of the psoc integrated circuit and presents specific pin, register , and electrical specifications. for in depth information, along with detailed programming infor - mation, refer to the psoc mixed signal array technical refer - ence manual on the web at http://www.cypress.com/psoc . for up to date ordering, packaging, and electrical specification information, refer to the latest psoc device datasheets on the web at http://www.cypress.com . development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store contains development kits, c compilers, and all accessories for psoc development. go to the cypress online store web site at http://www.cypress.com , click the online store shopping cart icon at the bottom of the web page and click psoc (program - mable system-on-chip) to view a current list of available items. technical training modules free psoc technical training modules are available for new users to psoc. training modules cover designing, debugging, advanced analog, and capsense. go to http://www.cypress. com/techtrain . consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to http://www.cypress.com , click on design support located on the left side of the web page and select cypros consultants. technical support psoc application engineers take pride in fast and accurate response. they are availabl e with a four hour guaranteed response at http://www.cypress.c om/support/login.cfm . application notes a long list of application notes a ssist you in every aspect of your design effort. to view the pso c application notes, go to the http://www.cypress.com and select application notes under the design resources list located in the center of the web page. application notes are so rted by date by default. development tools psoc designer is a microsoft ? windows based, integrated development environment for the programmable sys - tem-on-chip (psoc) devices. the psoc designer ide and application runs on windows nt 4.0, windows 2000, windows millennium (me), or windows xp. for more information, see figure 2 on page 4 . psoc designer helps the customer to select an operating con - figuration for the psoc, write application code that uses the psoc, and debug the ap plication. this syst em provides design database management by project, an integrated debugger with in-circuit emulator, in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high level c language compiler developed specifically for the devices in the family. [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 4 of 34 figure 2. psoc designer subsystems psoc designer software subsystems device editor the device editor subsystem enables the user to select different on board analog and digital components called user modules using the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. the device editor also supports easy development of multiple configurations and dynamic rec onfiguration. dynamic reconfig - uration enables changing configurations at run time. psoc designer sets up power on initialization tables for selected psoc block configurations and creates source code for an application framework. the framework contains software to operate the selected components. if the project uses more than one operating configuration, then it contains routines to switch between different sets of psoc block configurations at run time. psoc designer prints out a configuration sheet for a given project configuration for use during application program - ming in conjunction with the de vice datasheet. once the frame - work is generated, the user ad ds application specific code to flesh out the framework. it is also possible to change the selected components and r egenerate the framework. application editor application editor edits c language and assembly language source code. it also assemble s, compiles, links, and builds. assembler the macro assembler enables the assembly code for seamless merging with c code. the link libraries automatically use abso - lute addressing or are compiled in relative mode and linked with other software modules to get absolute addressing. c language compiler c language compiler supports the psoc family of devices. it quickly enables you to create complete c programs for the psoc family devices. the embedded optimizing c compiler provides all the features of c language tailored to the psoc architecture. it comes com - plete with embedded libraries providing port and bus opera - tions, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, enabling the designer to test the program in a physical system while providing an internal view of the psoc device. debugger commands enable the designer to read the program, read and write data memory, read and write io regis - ters, read and write cpu registers, set and clear breakpoints, and provide program run, halt , and step control. the debugger also enables the designer to cr eate a trace buffer of registers and memory locati ons of interest. online help system the online help system displays online and context sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its own context sensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer to get started. hardware tools in-circuit emulator a low cost, high functionality ic e (in-circuit emulator) is avail - able for development support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. commands results psoc designer core engine psoc configuration sheet manufacturing information file device database importable design database graphical designer interface context sensitive help project database application database user modules library psoc designer [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 5 of 34 designing with user modules the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware bl ocks give the psoc architecture a unique flexibility. it pays dividends in managing specification change during development and by lowering inventory costs. these configurable resources are called psoc blocks. they implement a wide variety of user selectable functions. each block has several registers to determine their function and con - nectivity to other blocks, multiple xers, buses, and to the io pins. iterative development cycles permit you to adapt the hardware and the software. this substantially lowers the risk of selecting a different part to meet the final design requirements. to speed the development proces s, the psoc designer inte - grated development environment (ide) provides a library of pre-built and pre-tested hardware peripheral functions called as user modules. user modules make selecting and implementing peripheral devices simple. they come in analog, digital, and mixed signal varieties. each user module establishes the basic register settings to implement the selected function. it also provides parameters to tailor its precise configuration to a particular application. for example, a pulse width modulator user module configures one or more digital psoc blocks, one for each 8-bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. user modules also provide tested soft - ware to cut the development time . the user module application programming interface (api) provides high level functions to control and respond to hardware events at run time. the api also provides optional interrupt service routines to adapt as needed. the api functions are document ed in user module datasheets that are viewed directly in the psoc designer ide. these datasheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter and docu - ments the setting of each register controlled by the user mod - ule. the development process starts when you open a new project and bring up the device editor, a graphical user interface (gui) for configuring the hardware. se lect the user modules you need for your project and map them on to the psoc blocks with point-and-click simplicity. then, build signal chains by intercon - necting the user modules to each other and the io pins. at this stage, configure the clock source connections and enter param - eter values directly or by selecting values from the drop down menus. when the hardware configuration is ready for testing or moves on to developing code for the project, perform the ?gen - erate application? step. the psoc designer generates the source code that automatically configures the device to your specification and provides the high level user module api func - tions. figure 3. user module and source code development flows now write the main program an d any sub-routines using psoc designer?s application editor su bsystem. the application edi - tor includes a project manager that enables to open the project source code files (including all generated code files) from a hierarchal view. the source code editor provides syntax color - ing and advanced edit features for both c and assembly lan - guage. file search capabilities include simple string searches and recursive ?grep-style? pa tterns. a single mouse click invokes the build manager. it employs a professional strength ?makefile? system to automatically analyze all file dependencies and run the compiler and assembler as necessary. project level options control optimization strategies used by the compiler and linker. syntax errors are displayed in a console window. double click the error message to show the offending line of source code. when all is correct, the linker builds a hex file image suit - able for programming. the last step in the development process takes place inside the psoc designer?s debugger su bsystem. the debugger down - loads the hex image to the in-cir cuit emulator (ice) where it runs at full speed. debugger ca pabilities rival those of systems costing many times more. in addition to traditional single step, run-to-breakpoint, and watch variable features, the debugger provides a large trace buffer. this enables to define complex breakpoint events such as monitoring address and data bus values, memory locations, and external signals. debugger interface to ice application editor device editor project manager source code editor storage inspector user module selection placement and parameter -ization generate application build all event & breakpoint manager build manager source code generator [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 6 of 34 document conventions acronyms used the following table lists the acrony ms that are used in this doc - ument. units of measure a units of measure table is located in the electrical specifica - tions section. table 6 on page 13 lists all the abbreviations used to measure the psoc devices. numeric naming hexadecimal numbers are represented with all letters in upper - case with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers are also represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b or 01000011b). numbers not indicated by an ?h?, ?b?, or 0x are dec - imals. acronym description ac alternating current api application programming interface cpu central processing unit dc direct current gpio general purpose io gui graphical user interface ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input or output lsb least significant bit lvd low voltage detect msb most significant bit por power on reset ppor precision power on reset psoc? programmable system-on-chip? slimo slow imo sram static random access memory [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 7 of 34 pinouts this section describes, lists, and illustrates the cy8c20234, cy8c20334, CY8C20434, and cy8c20534 psoc device pins and pinout configurations. the cy8c20x34 psoc device is available in a variety of packages th at are listed and shown in the following tables. every port p in (labeled with a ?p?) is capable of digital io and connection to th e common analog bus. however, vss, vdd, and xres are not capa - ble of digital io. 16-pin part pinout figure 4. cy8c20234 16-pin psoc device qfn (top view) ai, p2[5] ai, i2c scl, spi ss, p1[7] ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] 1 2 3 4 11 10 9 16 15 14 13 p0[3], ai p0[7], ai vdd p0[4], ai clk, i2c scl, spi mosi p1[1] ai, data, i2c sda, p1[0] p1[2], ai ai, p2[1] p1[4], ai, extclk xres p0[1], ai vss 12 5 6 7 8 table 1. 16-pin part pinout (qfn [2] ) pin no. type name description digital analog 1 io i p2[5] 2 io i p2[1] 3 ioh i p1[7] i 2 c scl, spi ss. 4 ioh i p1[5] i 2 c sda, spi miso. 5 ioh i p1[3] spi clk. 6 ioh i p1[1] clk [1] , i 2 c scl, spi mosi. 7 power vss ground connection. 8 ioh i p1[0] data [1] , i 2 c sda. 9 ioh i p1[2] 10 ioh i p1[4] optional external clock input (extclk). 11 input xres active high external reset with internal pull down. 12 io i p0[4] 13 power vdd supply voltage. 14 io i p0[7] 15 io i p0[3] integrating input. 16 io i p0[1] a = analog, i = input, o = output, oh = 5 ma high output drive notes 1. these are the issp pins, that are not high z at por (power on reset). see the psoc mixed signal array technical reference manual for details. 2. the center pad on the qfn package is connected to ground (vss) for best mechanical, thermal, a nd electrical performance. if n ot connected to ground, it is electrically floated and not connected to any other signal. [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 8 of 34 24-pin part pinout figure 5. cy8c20334 24-pin psoc device qfn (top view) ai, p2[5] ai, i2c scl, spi ss, p1[7] ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[2], ai p0[0], ai 24 23 22 21 20 19 p0[3], ai p0[5], ai p0[7], ai vdd p0[4], ai 7 8 9 10 11 12 spi mosi, p1[1] ai, data*, i2c sda, p1[0] ai, p1[2] ai, p2[3] ai, p2[1] nc p1[6], ai ai, extclk, p1[4] xres p2[0], ai p0[6], ai ai, clk*, i2c scl p0[1], ai vss table 2. 24-pin part pinout (qfn [2] ) pin no. type name description digital analog 1 io i p2[5] 2 io i p2[3] 3 io i p2[1] 4 ioh i p1[7] i 2 c scl, spi ss. 5 ioh i p1[5] i 2 c sda, spi miso. 6 ioh i p1[3] spi clk. 7 ioh i p1[1] clk [1] , i 2 c scl, spi mosi. 8 nc no connection. 9 power vss ground connection. 10 ioh i p1[0] data [1] , i 2 c sda. 11 ioh i p1[2] 12 ioh i p1[4] optional external clock input (extclk). 13 ioh i p1[6] 14 input xres active high external reset with internal pull down. 15 io i p2[0] 16 io i p0[0] 17 io i p0[2] 18 io i p0[4] 19 io i p0[6] analog bypass. 20 power vdd supply voltage. 21 io i p0[7] 22 io i p0[5] 23 io i p0[3] integrating input. 24 io i p0[1] cp power vss center pad is connected to ground. a = analog, i = input, o = output, oh = 5 ma high output drive [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 9 of 34 28-pin part pinout figure 6. cy8c20534 28-pin psoc device a, i, m, p0[7] a, i, m, p0[5] a, i, m, p0[3] a, i, m, p0[1] m, p2 [7 ] m, p2 [5 ] m, p2 [3 ] m, p2 [1 ] vss m, i2c scl, p1[7] m, i2c sda, p1[5] m, p1 [3 ] m, i2c scl, p1[1] vss vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m p0[0], a, i, m p2[6], m p2[4], m p2[2], m p2[0], m xres p1[6], m p1[4], extclk, m p1[2], m p1[0], i2c sda, m ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 table 3. 28-pin part pinout (ssop ) pin no. type name description digital analog 1 io i, m p0[7] analog column mux input. 2 io i, m p0[5] analog column mux input and column output. 3 io i, m p0[3] analog column mux input and column output, integrating input. 4 io i, m p0[1] analog column mux input, integrating input. 5 io m p2[7] 6 io m p2[5] 7 io i, m p2[3] direct switched capacitor block input. 8 io i, m p2[1] direct switched capacitor block input. 9 power vss ground connection. 10 io m p1[7] i2c serial clock (scl). 11 io m p1[5] i2c serial data (sda). 12 io m p1[3] 13 io m p1[1] i2c serial clock (scl), issp-sclk [1] . 14 power vss ground connection. 15 io m p1[0] i2c serial data (sda), issp-sdata [1] . 16 io m p1[2] 17 io m p1[4] optional external clock input (extclk). 18 io m p1[6] 19 input xres active high external reset with internal pull down. 20 io i, m p2[0] direct switched capacitor block input. 21 io i, m p2[2] direct switched capacitor block input. 22 io m p2[4] 23 io m p2[6] 24 io i, m p0[0] analog column mux input. 25 io i, m p0[2] analog column mux input. 26 io i, m p0[4] analog column mux input 27 io i, m p0[6] analog column mux input. 28 power vdd supply voltage. a = analog, i = input, o = output, oh = 5 ma high output drive. [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 10 of 34 32-pin part pinout figure 7. CY8C20434 32-pin psoc device ai, p0[1] ai, p2[7] ai, p2[5] ai, p2[3] ai, p2[1] ai, p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], ai p0[7], ai vdd p0[6], ai p0[4], ai p0[2], ai ai, p3[1] spi ss, p1[7] p0[0], ai p2[6], ai p3[0], ai xres ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] ai, clk*, i2c scl, spi mosi, p1[1] vss ai, data*, i2c sda, p1[0] ai, p1[2] ai, extclk, p1[4] ai, p1[6] p2[4], ai p2[2], ai p2[0], ai p3[2], ai p0[5], ai ai, i2c scl table 4. 32-pin part pinout (qfn [2] ) pin no. type name description digital analog 1 io i p0[1] 2 io i p2[7] 3 io i p2[5] 4 io i p2[3] 5 io i p2[1] 6 io i p3[3] 7 io i p3[1] 8 ioh i p1[7] i 2 c scl, spi ss. 9 ioh i p1[5] i 2 c sda, spi miso. 10 ioh i p1[3] spi clk. 11 ioh i p1[1] clk [1] , i 2 c scl, spi mosi. 12 power vss ground connection. 13 ioh i p1[0] data [1] , i 2 c sda. 14 ioh i p1[2] 15 ioh i p1[4] optional external clock input (extclk). 16 ioh i p1[6] 17 input xres active high external reset with internal pull down. 18 io i p3[0] 19 io i p3[2] 20 io i p2[0] 21 io i p2[2] 22 io i p2[4] 23 io i p2[6] 24 io i p0[0] 25 io i p0[2] 26 io i p0[4] 27 io i p0[6] analog bypass. [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 11 of 34 48-pin ocd part pinout the 48-pin qfn part table and pin diagram is for the cy8c2000 0 on-chip debug (ocd) psoc device. this part is only used for in-circuit debugging. it is not available for production. figure 8. cy8c20000 ocd psoc device 28 power vdd supply voltage. 29 io i p0[7] 30 io i p0[5] 31 io i p0[3] integrating input. 32 power vss ground connection. cp power vss center pad is connected to ground. a = analog, i = input, o = output, oh = 5 ma high output drive. table 4. 32-pin part pinout (qfn [2] ) (continued) ocd qfn (top view) nc vss p0[3], ai p0[5], ai p0[7], ai ocde ocdo vdd p0[6], ai nc nc nc 10 11 12 nc ai, p0[1] ai, p2[7] ai, p2[5] ai, p2[3] ai, p2[1] ai, p3[3] ai, p3[1] ai, i2c scl, spi ss, p1[7] ai, i2c sda, spi miso, p1[5] nc nc 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p0[2], ai p0[0], ai p2[6], ai p2[4], ai p2[2], ai p2[0], ai p3[2], ai p3[0], ai xres p1[6], ai p1[4], extclk, ai p0[4], ai 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 nc nc ai, spi clk, p1[3] ai, clk*, i2c scl, spi mosi, p1[1] vss cclk hclk ai, data*, i2c sda, p1[0] ai, p1[2] nc nc nc table 5. 48-pin ocd part pinout (qfn [2] ) pin no. digital analog name description 1 nc no connection. 2 io i p0[1] 3 io i p2[7] 4 io i p2[5] 5 io i p2[3] 6 io i p2[1] 7 io i p3[3] 8 io i p3[1] 9 ioh i p1[7] i 2 c scl, spi ss. 10 ioh i p1[5] i 2 c sda, spi miso. [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 12 of 34 11 io i p0[1] 12 nc no connection. 13 nc no connection. 14 nc no connection. 15 nc no connection. 16 ioh i p1[3] spi clk. 17 ioh i p1[1] clk [1] , i 2 c scl, spi mosi. 18 power vss ground connection. 19 cclk ocd cpu clock output. 20 hclk ocd high speed clock output. 21 ioh i p1[0] data [1] , i 2 c sda. 22 ioh i p1[2] 23 nc no connection. 24 nc no connection. 25 nc no connection. 26 ioh i p1[4] optional external clock input (extclk). 27 ioh i p1[6] 28 input xres active high external reset with internal pull down. 29 io i p3[0] 30 io i p3[2] 31 io i p2[0] 32 io i p2[2] 33 io i p2[4] 34 io i p2[6] 35 io i p0[0] 36 io i p0[2] 37 nc no connection. 38 nc no connection. 39 nc no connection. 40 io i p0[6] analog bypass. 41 power vdd supply voltage. 42 ocdo ocd odd data output. 43 ocde ocd even data io. 44 io i p0[7] 45 io i p0[5] 46 io i p0[3] integrating input. 47 power vss ground connection. 48 nc no connection. cp power vss center pad is connected to ground. a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive. table 5. 48-pin ocd part pinout (qfn [2] ) (continued) pin no. digital analog name description [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 13 of 34 electrical specifications this section presents the dc and ac electrical specifications of the cy8c20234, cy8c20334, CY8C20434, and cy8c20534 psoc devices. for the latest electrical specifications, che ck the most recent datasheet by visiting the web at http://www.cypress.com/psoc . specifications are valid for -40 o c t a 85 o c and t j 100 o c as specified, except where mentioned. refer to table 16 on page 19 for the electrical specificat ions on the internal main o scillator (imo) using slimo mode. figure 9. voltage versus cpu frequency and imo frequency trim options ta b l e 6 lists the units of measure t hat are used in this section. table 6. units of measure symbol unit of measure symbol unit of measure o c degree celsius w microwatts db decibels ma milliampere ff femto farad ms millisecond hz hertz mv millivolts kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k kilohm w ohm mhz megahertz pa picoampere m megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond sps samples per second v microvolts s sigma: one standard deviation vrms microvolts root-mean-square v volts 5.25 4.75 3.00 750 khz 12 mhz cpu frequency vdd voltage 5.25 4.75 3.00 750 khz 6 mhz 12 mhz imo frequency vdd voltage 3.60 3 mhz 2.40 slimo mode=1 2.40 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slimo mode=0 slimo mode=1 slimo mode=0 2.70 slimo mode=1 slimo mode=0 2.70 6 mhz [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 14 of 34 absolute maximum ratings operating temperature table 7. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 25 +100 o c higher storage temperatures reduces data retention time. recommended storage temperature is +25 o c 25 o c. extended duration storage tempera - tures above 65 o c degrades reliability. t a ambient temperature with power applied -40 ? +85 o c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current in to any port pin -25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma table 8. operat ing temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 o c t j junction temperature -40 ? +100 o c the temperature rise from ambient to junction is package specific. see table 14 on page 17 . the user must limit the power consumption to comply with this requirement. [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 15 of 34 dc electrical characteristics dc chip level specifications ta b l e 9 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. dc general purpose io specifications unless otherwise noted, the ta b l e 10 lists guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75v to 5.25v and -40c ta 85c, 3.0v to 3.6v and -40c ta 85c, or 2.4v to 3.0v and -40c ta 85c, respec - tively. typical parameters apply to 5v, 3.3v, and 2.7v at 25c. these are for design guidance only. table 9. dc chip level specifications sym - bol description min typ max units notes vdd supply voltage 2.40 ? 5.25 v see ta b l e 14 on page 17 . i dd12 supply current, imo = 12 mhz ? 1.5 2.5 ma conditions are vdd = 3.0v, t a = 25 o c, cpu = 12 mhz. i dd6 supply current, imo = 6 mhz ? 1 1.5 ma conditions are vdd = 3.0v, t a = 25 o c, cpu = 6 mhz. i sb27 sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. mid temperature range. ? 2.6 4. a vdd = 2.55v, 0 o c t a 40 o c. i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 2.8 5 a vdd = 3.3v, -40 o c t a 85 o c. table 10. 5v and 3.3v dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k v oh1 high output voltage port 0, 2, or 3 pins vdd - 0.2 ? ? v ioh < 10 a, vdd > 3.0v, maximum of 20 ma source current in all ios. v oh2 high output voltage port 0, 2, or 3 pins vdd - 0.9 ? ? v ioh = 1 ma, vdd > 3.0v, maximum of 20 ma source current in all ios. v oh3 high output voltage port 1 pins with ldo regulator disabled vdd - 0.2 ? ? v ioh < 10 a, vdd > 3.0v, maximum of 10 ma source current in all ios. v oh4 high output voltage port 1 pins with ldo regulator disabled vdd - 0.9 ? ? v ioh = 5 ma, vdd > 3.0v, maximum of 20 ma source current in all ios. v oh5 high output voltage port 1 pins with 3.0v ldo regulator enabled 2.75 3.0 3.2 v ioh < 10 a, vdd > 3.1v, maximum of 4 ios all sourcing 5 ma. v oh6 high output voltage port 1 pins with 3.0v ldo regulator enabled 2.2 ? ? v ioh = 5 ma, vdd > 3.1v, maximum of 20 ma source current in all ios. v oh7 high output voltage port 1 pins with 2.4v ldo regulator enabled 2.1 2.4 2.5 v ioh < 10 a, vdd > 3.0v, maximum of 20 ma source current in all ios. v oh8 high output voltage port 1 pins with 2.4v ldo regulator enabled 2.0 ? ? v ioh < 200 a, vdd > 3.0v, maximum of 20 ma source current in all ios. v oh9 high output voltage port 1 pins with 1.8v ldo regulator enabled 1.6 1.8 1.95 v ioh < 10 a. 3.0v vdd 3.6v. 0 o c ta 85 o c. maximum of 20 ma source current in all ios. [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 16 of 34 v oh10 high output voltage port 1 pins with 1.8v ldo regulator enabled 1.5 ? ? v ioh < 100 a. 3.0v vdd 3.6v. 0 o c ta 85 o c. maximum of 20 ma source current in all ios. v ol low output voltage ? ? 0.75 v iol = 20 ma, vdd > 3.0v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]). v il input low voltage ? ? 0.8 v 3.6v vdd 5.25v. v ih input high voltage 2.0 ? v 3.6v vdd 5.25v. v h input hysteresis voltage ? 140 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input 0.5 1.7 5 pf package and pin dependent temper - ature = 25 o c. c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent temper - ature = 25 o c. table 10. 5v and 3.3v dc gp io specifications (continued) table 11. 2.7v dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k v oh1 high output voltage port 1 pins with ldo regulator disabled vdd - 0.2 ? ? v ioh < 10 a, maximum of 10 ma source current in all ios. v oh2 high output voltage port 1 pins with ldo regulator disabled vdd - 0.5 ? ? v ioh = 2 ma, maximum of 10 ma source current in all ios. v ol low output voltage ? ? 0.75 v iol = 10 ma, maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]). v olp1 low output voltage port 1 pins ? ? 0.4 v iol=5 ma maximum of 50 ma sink current on even port pins (for example, p0[2] and p3[4]) and 50 ma sink current on odd port pins (for example, p0[3] and p2[5]). 2.4v vdd < 3.6v. v il input low voltage ? ? 0.75 v 2.4v vdd < 3.6v. v ih1 input high voltage 1.4 ? ? v 2.4v vdd < 2.7v. v ih2 input high voltage 1.6 ? ? v 2.7v vdd < 3.6v. v h input hysteresis voltage ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input 0.5 1.7 5 pf package and pin dependent temper - ature = 25 o c. c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent temper - ature = 25 o c. [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 17 of 34 dc analog mux bus specifications ta b l e 12 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. dc low power comparator specifications ta b l e 13 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v at 25 c. these are for design guidance only. dc por and lvd specifications ta b l e 14 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 12. dc analog mux bus specifications symbol description min typ max units notes r sw switch resistance to common analog bus ? ? 400 800 w w vdd 2.7v 2.4v vdd 2.7v table 13. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? vdd ? 1 v i slpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv table 14. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 vdd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 2.36 2.60 2.82 2.40 2.65 2.95 v v v vdd is greater than or equal to 2.5v during startup, reset from the xres pin, or reset from watchdog. v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.39 2.54 2.75 2.85 2.96 ? ? 4.52 2.45 2.71 2.92 3.02 3.13 ? ? 4.73 2.51 [3] 2.78 [4] 2.99 [5] 3.09 3.20 ? ? 4.83 v v v v v v v v notes 3. always greater than 50 mv above v ppor (porlev = 00) for falling supply. 4. always greater than 50 mv above v ppor (porlev = 01) for falling supply. 5. always greater than 50 mv above v ppor (porlev = 10) for falling supply. [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 18 of 34 dc programming specifications ta b l e 15 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 15. dc programming specifications symbol description min typ max units notes vdd iwrite supply voltage for flash write operations 2.70 ? ? v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd ?1.0 ? vdd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) [6] 1,800,0 00 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years note 6. a maximum of 36 x 50,000 block endurance cycles is allowed. this is balanced between operations on 36x1 blocks of 50,000 maxi mum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycl es each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 19 of 34 ac electrical characteristics ac chip level specifications ta b l e 16, table 17, and ta b l e 18 list guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c respectively. typ - ical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 16. 5v and 3.3v ac chip-level specifications symbol description min typ max units notes f cpu1 cpu frequency (3.3v nominal) 0.75 ? 12.6 mhz 12 mhz only for slimo mode = 0. f 32k1 internal low speed oscillator frequency 15 32 64 khz f imo12 internal main oscillator stability for 12 mhz (commercial temperature) [ 7 ] 11.4 12 12.6 mhz trimmed for 3.3v operation using factory trim values. see figure 2-1b, slimo mode = 0. f imo6 internal main oscillator stability for 6 mhz (commercial temperature) 5.70 6.0 6.30 mhz trimmed for 3.3v operation using factory trim values. see figure 2-1b, slimo mode = 1. dc imo duty cycle of imo 40 50 60 % t ramp supply ramp time 0 ? ? s t xrst external reset pulse width 10 ? ? s table 17. 2.7v ac chip level specifications symbol description min typ max units notes f cpu1 cpu frequency (2.7v nominal) 0.75 ? 3.25 mhz f 32k1 internal low speed oscillator frequency 8 32 96 khz f imo12 internal main oscillator stability for 12 mhz (commercial temperature) [ 7 ] 11.0 12 12.9 mhz trimmed for 2.7v operation using factory trim values. see figure 2-1b, slimo mode = 0. f imo6 internal main oscillator stability for 6 mhz (commercial temperature) 5.60 6.0 6.40 mhz trimmed for 2.7v operation using factory trim values. see figure 2-1b, slimo mode = 1. dc imo duty cycle of imo 40 50 60 % t ramp supply ramp time 0 ? ? s t xrst external reset pulse width 10 ? ? s table 18. 2.7v ac chip level specifications symbol description min typ max units notes f cpu1 cpu frequency (2.7v minimum) 0.75 ? 6.3 mhz f 32k1 internal low speed oscillator frequency 8 32 96 khz f imo12 internal main oscillator stability for 12 mhz (commercial temperature) [ 7 ] 11.0 12 12.9 mhz trimmed for 2.7v operation using factory trim values. see figure 2-1b, slimo mode = 0. note 7. 0 to 70 c ambient, vdd = 3.3 v. [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 20 of 34 ac general purpose io specifications ta b l e 19 and ta b l e 20 list guaranteed maximum and minimum specifications fo r the voltage and temperatur e ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. figure 10. gpio timing diagram f imo6 internal main oscillator stability for 6 mhz (commercial temperature) 5.60 6.0 6.40 mhz trimmed for 2.7v operation using factory trim values. see figure 2-1b, slimo mode = 1. dc imo duty cycle of imo 40 50 60 % t ramp supply ramp time 0 ? ? s t xrst external reset pulse width 10 ? ? s table 18. 2.7v ac chip level specifications (continued) symbol description min typ max units notes table 19. 5v and 3.3v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 6 mhz normal strong mode, port 1. trise023 rise time, strong mode, cload = 50 pf ports 0, 2, 3 15 ? 80 ns vdd = 3.0 to 3.6v and 4.75v to 5.25v, 10% - 90% trise1 rise time, strong mode, cload = 50 pf port 1 10 ? 50 ns vdd = 3.0 to 3.6v, 10% - 90% tfall fall time, strong mode, cload = 50 pf all ports 10 ? 50 ns vdd = 3.0 to 3.6v and 4.75v to 5.25v, 10% - 90% table 20. 2.7v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 1.5 mhz normal strong mode, port 1. trise023 rise time, strong mode, cload = 50 pf ports 0, 2, 3 15 ? 100 ns vdd = 2.4 to 3.0v, 10% - 90% trise1 rise time, strong mode, cload = 50 pf port 1 10 ? 70 ns vdd = 2.4 to 3.0v, 10% - 90% tfall fall time, strong mode, cload = 50 pf all ports 10 ? 70 ns vdd = 2.4 to 3.0v, 10% - 90% tfall trise023 trise1 90% 10% gpio pin output voltage [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 21 of 34 ac comparator amplifier specifications ta b l e 21 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. ac analog mux bus specifications ta b l e 22 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. ac low power comparator specifications ta b l e 23 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v at 25 c. these are for design guidance only. ac external clock specifications ta b l e 24 , table 25 , table 26 , and ta b l e 27 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respec - tively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 21. ac operational amplifier specifications symbol description min typ max units notes t comp comparator response time, 50 mv overdrive 100 200 ns ns vdd 3.0v. 2.4v < vcc < 3.0v. table 22. ac analog mux bus specifications symbol description min typ max units notes f sw switch rate ? ? 3.17 mhz table 23. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc . table 24. 5v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.750 ? 12.6 mhz ? high period 38 ? 5300 ns ? low period 38 ? ? ns ? power up imo to switch 150 ? ? s [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 22 of 34 table 25. 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.750 ? 12.6 mhz maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ? ns ? power up imo to switch 150 ? ? s table 26. 2.7v (nominal) ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.750 ? 3.08 0 mhz maximum cpu frequency is 3 mhz at 2.7v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.15 ? 6.35 mhz if the frequency of the external clock is greater than 3 mhz, the cpu clock divider is set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 160 ? 5300 ns ? low period with cpu clock divide by 1 160 ? ? ns ? power up imo to switch 150 ? ? s table 27. 2.7v (minimum) ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.750 ? 6.3 0 mhz maximum cpu frequency is 6 mhz at 2.7v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.15 ? 12.6 mhz if the frequency of the external clock is greater than 6 mhz, the cpu clock divider is set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 160 ? 5300 ns ? low period with cpu clock divide by 1 160 ? ? ns ? power up imo to switch 150 ? ? s [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 23 of 34 ac programming specifications ta b l e 28 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. ac spi specifications ta b l e 29 and ta b l e 30 list guaranteed maximum and minimum specifications fo r the voltage and temperatur e ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 28. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 15 ? ms t write flash block write time ? 30 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns 3.6 < vdd t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6 t dsclk2 data out delay from falling edge of sclk ? ? 70 ns 2.4 vdd 3.0 table 29. 5v and 3.3v ac spi specifications symbol description min typ max units notes f spim maximum input clock fr equency selection, master ? ? 6.3 mhz output clock frequency is half of input clock rate f spis maximum input clock fr equency selection, slave ? ? 2.05 mhz t ss width of ss_ negated between transmis - sions 50 ? ? ns table 30. 2.7v ac spi specifications symbol description min typ max units notes f spim maximum input clock frequency selection, master ? ? 3.15 mhz output clock frequency is half of input clock rate f spis maximum input clock frequency selection, slave ? ? 1.025 mhz t ss width of ss_ negated between transmis - sions 50 ? ? ns [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 24 of 34 ac i 2 c specifications ta b l e 31 and ta b l e 32 list guaranteed maximum and minimum specifications fo r the voltage and temperatur e ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c. these are for design guidance only. table 31. ac characteristics of the i 2 c sda and scl pins for vdd 3.0v symbol description standard mode fast mode units notes min max min max f scl i 2 c scl clock frequency 0 100 0 400 khz t hdsta i 2 c hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 ? 0.6 ? s t low i 2 c low period of the scl clock 4.7 ? 1.3 ? s t high i 2 c high period of the scl clock 4.0 ? 0.6 ? s t susta i 2 c setup time for a repeated start condition 4.7 ? 0.6 ? s t hddat i 2 c data hold time 0 ? 0 ? s t sudat i 2 c data setup time 250 ? 100 [8] ? ns t susto i 2 c setup time for stop condition 4.0 ? 0.6 ? s t buf i 2 c bus free time between a stop and start condition 4.7 ? 1.3 ? s t sp i 2 c pulse width of spikes are suppressed by the input filter ? ? 0 50 ns note 8. a fast mode i 2 c bus device is used in a standard mode i 2 c bus system but the requirement tsu; dat ? 250 ns is met. this automatically is the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line trmax + tsu; dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 25 of 34 figure 11. definition for timing for fast/standard mode on the i2c bus table 32. 2.7v ac characteristics of the i 2 c sda and scl pins (fast mode not supported) symbol description standard mode fast mode units notes min max min max f scl i 2 c scl clock frequency. 0 100 ? ? khz t hdsta i 2 c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? ? ? s t low i 2 c low period of the scl clock. 4.7 ? ? ? s t high i 2 c high period of the scl clock 4.0 ? ? ? s t susta i 2 c setup time for a repeated start condition. 4.7 ? ? ? s t hddat i 2 c data hold time. 0 ? ? ? s t sudat i 2 c data setup time. 250 ? ? ? ns t susto i 2 c setup time for stop condition. 4.0 ? ? ? s t buf i 2 c bus free time between a stop and start condition. 4.7 ? ? ? s t sp i 2 c pulse width of spikes are suppressed by the input filter. ? ? ? ? ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 26 of 34 packaging dimensions this section illustrates the packaging specifications for t he cy8c20234, cy8c20334, CY8C20434, and cy8c20534 psoc devices along with the thermal impedances for each package. it is important to note t hat emulation tools require a larger area on the ta rget pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress. com/design/mr10161 . figure 12. 16-pin (3x3 mm x 0.6 max) qfn 001-09116 *c [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 27 of 34 figure 13. 24-pin (4x4 x 0.6 mm) qfn figure 14. 28-lead (210-mil) ssop 001-13937 *a 51-85079 *c [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 28 of 34 figure 15. 32-pin (5x5 mm 0.60 max) qfn 001-06392 *a [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 29 of 34 figure 16. 48-pin (7x7 mm) qfn for information on the preferred dimensions for mounting the qfn packages, see the following application note at http://www. amkor.com/products/notes_papers/mlfappnote.pdf. it is important to note that pinned vias for thermal conductio n are not required for the low power 24-, 32-, and 48-pin qfn pso c devices. 001-12919 *a [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 30 of 34 thermal impedances solder reflow peak temperature ta b l e 34 illustrates the minimum solder reflow peak tempera - ture to achieve good solderability. development tool selection software psoc designer? at the core of the psoc development software suite is psoc designer. this is used by thou sands of psoc developers. this robust software is facilitating psoc designs for half a decade. psoc designer is available free of charge at http://www.cypress.com under design r esources >> soft - ware and drivers. psoc express? as the latest addition to the pso c development software suite, psoc express is the first visual embedded system design tool that enables a user to create an entire psoc project and gener - ate a schematic, bom, and datas heet without writing a single line of code. users work direct ly with application objects such as leds, switches, sensors, and fans. psoc express is avail - able free of charge at http://www.cypress .com/psocexpress. psoc programmer psoc programmer is flexible enough and is used on the bench in development and also suitable for factory programming. psoc programmer works either as a standalone programming application or operates directly from psoc designer or psoc express. psoc progra mmer software is compatible with both psoc ice cube in-circuit emul ator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.co m/psocprogrammer. cy3202-c imagecraft c compiler cy3202 is the optional upgrade to psoc designer that enables the imagecraft c compiler. it is available at the cypress online store. at http://www.cypress.com , click the online store shop - ping cart icon at the bottom of the web page and click psoc (programmable system-on-chip) to view a current list of avail - able items. development kits all development kits are sold at the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyp ing and development with psoc designer. this kit supports in-cir cuit emulation and the software interface enables users to run, halt, and single step the proces - sor and view the content of specific memory locations. psoc designer supports the advance em ulation features also. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66 family cat-5 adapter mini-eval programming board 110 ~ 240v power supply, euro-plug adapter imagecraft c compiler (registration required) issp cable usb 2.0 cable and blue cat-5 cable 2 cy8c29466-24pxi 28-pdip chip samples table 33. thermal impedances per package package typical ja [9] 16 qfn 46 o c/w 24 qfn [10] 25 o c/w 28 ssop [10] 96 o c/w 32 qfn [10] 27 o c/w 48 qfn [10] 28 o c/w table 34. solder reflow peak temperature package minimum peak temperature [11] maximum peak temperature 16 qfn 240 o c 260 o c 24 qfn 240 o c 260 o c 28 ssop 240 o c 260 o c 32 qfn 240 o c 260 o c 48 qfn 240 o c 260 o c notes 9. t j = t a + power x ja. 10. to achieve the thermal impedance specified for the ** package, the center thermal pad is soldered to the pcb ground plane. 11. higher temperatures is required based on the solder melting point. typical temperatures for solder are 220 5oc with sn-pb or 245 5oc with sn-ag-cu paste. refer to the solder manufacturer specifications. [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 31 of 34 cy3210-expressdk psoc express development kit the cy3210-expressdk is for advanced prototyping and devel - opment with psoc express (us ed with ice-cube in-circuit emulator). it provides access to i 2 c buses, voltage reference, switches, upgradeable modules, and more. the kit includes: psoc express software cd express development board four fan modules two proto modules miniprog in-system serial programmer minieval pcb evaluation board jumper wire kit usb 2.0 cable serial cable (db9) 110 ~ 240v power supply, euro-plug adapter 2 cy8c24423a-24pxi 28-pdip chip samples 2 cy8c27443-24pxi 28-pdip chip samples 2 cy8c29466-24pxi 28-pdip chip samples evaluation tools all evaluation tools are sold at the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit enables the user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiomete r, leds, and plenty of bread - boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3214-psocevalusb the cy3214-psocevalusb evaluation kit features a develop - ment board for the cy8c24794-24lfxi psoc device. special features of the board include both usb and capacitive sensing development and debugging support. this evaluation board also includes an lcd module, potentiometer, leds, an enunci - ator and plenty of bread boarding sp ace to meet all of your eval - uation needs. the kit includes: psocevalusb board lcd module miniprog programming unit mini usb cable psoc designer and example projects cd getting started guide wire pack device programmers all device programmers are purchased from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular pro - grammer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base 3 programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 32 of 34 cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes pro - tection circuitry and an industrial case that is more robust than the miniprog in a production programming environment. note that cy3207issp needs special software and is not com - patible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240v power supply, euro-plug adapter usb 2.0 cable accessories (emulation and programming) third party tools several tools are specially designed by the following third party vendors to accompany psoc devices during development and production. specific details of each of these tools are found at http://www.cypress.com under design resources >> eval - uation boards. build a psoc emulator into your board for details on emulating the circuit before going to volume pro - duction using an on-chip debug (ocd) non-production psoc device, see application note ?debugging - build a psoc emu - lator into your board - an2323? at http://www.cypress. com/design/an2323 . table 35. emulation and programming accessories part number pin package flex-pod kit [12] foot kit [13] prototyping module adapter [14] cy8c20234-12lkxi 16 soic - cy3250-16qfn-fk cy3210-0x34 - cy8c20334-12lqxi 24 qfn cy3250-20334qfn cy3250-24qfn-fk cy3210-0x34 as-24-28-01ml-6 cy8c20534-12pvxi 28 ssop - cy3250-28ssop-fk cy3210-0x34 - CY8C20434-12lkxi 32 qfn cy3250-20434qfn cy3250-32qfn-fk cy3210-0x34 as-32-28-03ml-6 notes 12. flex-pod kit includes a practice flex-pod and a practice pcb, in addition to two flex-pods. 13. foot kit includes surface mount feet that is soldered to the target pcb. 14. programming adapter converts non-dip package to dip footprint. specific details and ordering information for each of the ada pters is found at http://www.emulation.com . [+] feedback
cy8c20534, CY8C20434 cy8c20334, cy8c20234 document number: 001-05356 rev. *d page 33 of 34 ordering information ta b l e 36 lists the cy8c20234, cy8c20334, cy 8c20434, and cy8c20534 psoc device?s key package features and ordering codes. figure 17. ordering code definitions table 36. psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) digital blocks capsense blocks digital io pins analog inputs [15] analog outputs xres pin 16-pin (3x3 mm 0.60 max) qfn cy8c20234-12lkxi 8k 512 0 1 13 13 [15] 0 yes 16-pin (3x3 mm 0.60 max) qfn (tape and reel) cy8c20234-12lkxit 8k 512 0 1 13 13 [15] 0 yes 24-pin (4x4 mm 0.60 max) qfn cy8c20334-12lqxi 8k 512 0 1 20 20 [15] 0 yes 24-pin (4x4 mm 0.60 max) qfn (tape and reel) cy8c20334-12lqxit 8k 512 0 1 20 20 [15] 0 yes 28-pin (210-mil) ssop cy8c20534-pvxi 8k 512 0 1 24 24 0 yes 28-pin (210-mil) ssop (tape and reel) cy8c20534-pvxit 8k 512 0 1 24 24 0 yes 32-pin (5x5 mm 0.60 max) qfn CY8C20434-12lkxi 8k 512 0 1 28 28 [15] 0 yes 32-pin (5x5 mm 0.60 max) qfn (tape and reel) CY8C20434-12lkxit 8k 512 0 1 28 28 [15] 0 yes 48-pin ocd qfn [16] cy8c20000-12lfxi 8k 512 0 1 28 28 [15] 0 yes cy 8 c 20 xxx- 12 xx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx = qfn pb-free lkx/lqx = qfn pb-free ax = tqfp pb-free speed: 12 mhz part number family code technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress notes 15. dual function digital io pins also connect to the common analog mux. 16. this part may be used for in-circuit debugging. it is not available for production. [+] feedback

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